Lesson 4.7.1.1

4.7.1.1 Internal hardware components Quiz: AQA Computer Science, Unit 7

20 questions

Written by Revision Ninja · Last reviewed 11 October 2026

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Lesson 4.7.1.1, Internal hardware components: 20 multiple choice questions for the AQA Computer Science (7517), Unit 7: Fundamentals of computer organisation and architecture, written with Revision Ninja.

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The 20 questions

  1. Which bus carries the memory address to be accessed by the processor?

    • Control bus
    • System bus
    • Address bus
    • Data bus

  2. Which bus carries command and timing signals between computer components?

    • Data bus
    • Control bus
    • Expansion bus
    • Address bus

  3. In von Neumann architecture, what do data and instructions share?

    • Same main memory
    • Independent buses
    • Dedicated registers
    • Separate caches

  4. Which type of system commonly uses a Harvard architecture processor?

    • Embedded systems
    • Cloud servers
    • Mainframe computers
    • Desktop computers

  5. A processor has an address bus of 16 lines and each memory location holds one byte. How many distinct locations can it address?

    • 65,536 (2^16)
    • 32,768 (2^15)
    • 16,384 (2^14)
    • 131,072 (2^17)

  6. A byte-addressable system has 32 address lines. What is its maximum memory capacity?

    • 8 GB
    • 4 GB
    • 2 GB
    • 16 GB

  7. A system uses a 20-line address bus with byte addressing. How many locations can it address?

    • 524,288
    • 20,000
    • 2,097,152
    • 1,048,576

  8. Which component holds the data and programs currently in use by the processor?

    • Cache controller
    • Main memory
    • Secondary storage
    • Hard drive

  9. What is the primary benefit of using shared buses over point-to-point connections?

    • Zero power consumption
    • Unlimited bandwidth
    • Fewer connections
    • Increased clock speed

  10. What limits transfer speed in von Neumann architecture due to shared memory pathways?

    • Register spill
    • Harvard delay
    • Von Neumann bottleneck
    • Bus arbitration fault

  11. A processor has a 32-bit data bus and must read a 64-bit value from memory. How many separate data bus transfers are needed?

    • 2
    • 1
    • 4
    • 8

  12. In addressable memory, what identifies each unique location in main memory?

    • Register index
    • Control flag
    • Bus line number
    • Memory address

  13. A byte-addressable system requires 200,000 locations. What is the minimum number of address lines needed?

    • 19
    • 20
    • 17
    • 18

  14. What key performance advantage is offered by Harvard architecture over von Neumann?

    • Universal compatibility
    • Lower clock speed
    • Simultaneous access
    • Larger memory capacity

  15. Which component fetches, decodes, and executes instructions in a computer system?

    • Control bus
    • Main memory
    • I/O controller
    • Processor

  16. Which bus transmits read and write control signals between the processor and memory?

    • Control bus
    • Peripheral bus
    • Address bus
    • Data bus

  17. Which component manages communication between peripheral devices and the system bus?

    • Expansion slot
    • Control bus
    • I/O controller
    • Device driver

  18. How many unique memory locations can be directly addressed using a 40-line address bus?

    • 64^40
    • 2^40
    • 40^2
    • 2^64

  19. Which term describes computer memory that loses its contents when power is turned off?

    • Non-volatile
    • Read-only
    • Permanent
    • Volatile

  20. Which bus transfers memory address locations from the processor to main memory?

    • Address bus
    • System bus
    • Control bus
    • Data bus

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