Lesson 4.7.3.6

4.7.3.6 Interrupts Quiz: AQA Computer Science, Unit 7

20 questions

Written by Revision Ninja · Last reviewed 11 October 2026

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Lesson 4.7.3.6, Interrupts: 20 multiple choice questions for the AQA Computer Science (7517), Unit 7: Fundamentals of computer organisation and architecture, written with Revision Ninja.

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The 20 questions

  1. What signal causes the processor to pause its current execution cycle?

    • Polling request
    • Clock pulse
    • Reset vector
    • Interrupt

  2. What software routine is executed by the processor to handle a specific interrupt?

    • Interrupt service routine
    • Kernel process
    • System call
    • Device driver

  3. At what point in the fetch-execute cycle does the CPU check for pending interrupts?

    • Before decode
    • Start of fetch
    • During decode
    • End of execute

  4. What must be saved when an interrupt occurs so the CPU state is preserved?

    • Volatile environment
    • ROM contents
    • BIOS settings
    • Hard drive cache

  5. Which register's contents form part of the saved volatile environment during an interrupt?

    • Data bus
    • Status register
    • Address bus
    • Control bus

  6. Which event is an example of a hardware-generated interrupt signal?

    • Syntax error
    • Key press
    • Loop iteration
    • Variable assignment

  7. When is an interrupt signal checked during the fetch-execute cycle?

    • Middle of execution
    • During decode phase
    • End of cycle
    • Start of fetch

  8. What is the first step the processor takes upon accepting an interrupt?

    • Reset the PC
    • Clear main memory
    • Execute the ISR
    • Save volatile environment

  9. What alternative technique to interrupts repeatedly checks device status, wasting CPU time?

    • Pipelining
    • Polling
    • Paging
    • Caching

  10. What hardware component generates regular clock ticks to trigger system timer interrupts?

    • Arithmetic logic unit
    • Memory data register
    • Control unit
    • Programmable interval timer

  11. What critical data within the status register must be preserved during an interrupt?

    • Opcode values
    • Clock speed
    • Processor flags
    • Bus width

  12. A computer receives 50 interrupts per second, and each ISR takes 2 ms. What fraction of processor time is spent in ISRs?

    • 2%
    • 100%
    • 50%
    • 10%

  13. Why must an Interrupt Service Routine (ISR) execute as quickly as possible?

    • To format storage
    • To minimise delays
    • To clear cache
    • To prevent overheating

  14. Which specific data structure manages multiple interrupts arriving according to their priority levels?

    • Binary search tree
    • Hash table
    • Priority queue
    • Circular buffer

  15. Where is the volatile environment typically saved when handling an interrupt?

    • ROM chip
    • Hard disk
    • Control unit
    • System stack

  16. Why are register values defined as a volatile environment during an interrupt?

    • They change constantly
    • They use ROM
    • They are permanent
    • They consume power

  17. What main advantage do interrupts provide compared to device polling?

    • Expands RAM capacity
    • Saves CPU time
    • Increases clock speed
    • Reduces bus width

  18. What is saved to the stack before an interrupt service routine executes?

    • Volatile environment
    • Interrupt vector
    • Secondary storage
    • Cache contents

  19. At what point in the Fetch-Execute cycle are interrupts checked?

    • Fetch stage
    • Decode stage
    • Execute stage
    • End of cycle

  20. What structure is typically used to store register values during an interrupt?

    • System stack
    • Address bus
    • Accumulator
    • Disk cache

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